Other Non-Standard Layout Verification Checks Include:

• For new processes, we generate test layout that violates foundry rules to check that the Design Rule Check (DRC) program correctly finds the rule violations.
• We check that a poly jumper or other high resistance jumper is not in series with any resistor since this will change the resistor value.
• We check that the Bond Pad region is really connected to the internal circuits.
• Bonding angles are checked. If requested, we can generate a to scale bonding diagram showing the package, die and bonds.
• We check that a substrate region that is totally enclosed by a well (Like the hole in the donut) is never connected to a voltage different from the substrate. LVS programs will often ignore this case that could result in unwanted substrate current.
• We check that all mask layers are present in the data file sent to the foundry.
• We check that a layer does not exist in the foundry data file that could trigger the foundry not to make a mask. For example, a field implant mask will normally be generated by the foundry from the Nwell layer. If a single object on the field layer is found by the foundry, they may assume that the field mask exists in the layout data and they don't need to make it.
• We check that the LVS program does not allow the gate sequence to be switched on series Mosfets. This can be an important check to be sure analog cascoded transistors are done correctly.
• We check that no data exists outside of the chip boundry.
• If even a small layout change is made during the final checks, then the final checks must be repeated.
• We run all final checks on the actual data file sent to the foundry and if this data file is sent over the Internet, then we send a copy to our self and check that the file we receive is the same as the file sent.

Besides these checks, our standard checks include